倒数第四篇:附录 A ARM 指令集、ARM 寻址方式和 Thumb 指令集速查表
倒数第三篇:表 A –2 ARM 寻址方式速查表
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倒数第一篇:附录 B ARM 指令集编码和 Thumb 指令集编码
第一篇:嵌入式系统(修订本)——Intel XScale 结构与开发 陈章龙 著
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表A-3 Thumb 指令速查表

嵌入式系统(修订本)——Intel XScale 结构与开发 陈章龙 著

All Thumb registers are Lo (R0~R7) except where specified. Hi refisters are R8~R15

功能

§

汇编指令码

标志位

是否更新

Action

Notes

Mov

immediate

Lo to Lo

Hi to Lo ,Lo to Hi, Hi to Hi

MOV Rd , #<immed_8> MOV Rd , Rm

MOV Rd , Rm

×

Rd:=immed_8

Rd:=Rm

Rd:=Rm

8-bit immediate value

Not Lo to Lo

Arithmetic

Add

Lo to Lo

Hi to Lo ,Lo to Hi, Hi to Hi immediate

With carry

Value to SP

Form address from SP Form address from PC

subtract

Immediate 3

Immediate 8

With carry

Value to SP Negate

ADD Rd , Rn , #<immed_3> ADD Rd , Rn , Rm

ADD Rd , Rm

ADD Rd , #<immed_8> ADC Rd , Rm

ADD SP, #<immed_7*4>

ADD Rd , SP , #<immed_8*4> ADD Rd , PC , #<immed_7*4> SUB Rd , Rn , Rm

SUB Rd , Rn , #<immed_3> SUB Rd , #<immed_8>

SBC Rd , Rm

SUB SP , #<immed_7*4> NEG Rd , Rm

×

×

×

×

×

Rd:=Rn+immed_3

Rd:=Rn+Rm Rd:=Rd+Rm Rd:=Rn+immed_8

Rd:=Rn+Rm+C-bit

SP:=SP+immed_7*4

Rd:=SP+immed_8*4

Rd:=(PC AND 0xFFFFFFFC) +immed_8*4

Rd:=Rn-Rm

Rd:=Rn-immed_3

Rd:=Rn-immed_8

Rd:=Rn-Rm-NOT C-bit

SP:=SP-immed_7*4

Rd:= -Rm

3-bit immediate value

Not Lo to Lo

8-bit immediate value

9-bit immediate value(word-aligned )

10-bit immediate value(word-aligned )

10-bit immediate value(word-aligned )

3-bit immediate value

8-bit immediate value

9-bit immediate value(word-aligned )

508

Multiply

Compare Negative immediate

No operation

MUL Rd , Rm CMP Rd , Rm CMN Rd , Rm

CMP Rd , #<immed_8>

NOP

×

Rd:= Rm*Rd

Update CPSR Flags on Rn-Rm

Update CPSR Flags on Rn+Rm

Update CPSR Flags on Rn-immed_8

R8:=R8

Can Lo to Lo, Lo to Hi , Hi to Lo , or Hi to Hi

8-bit immediate value

Flags not affected

Logic

AND Exclusive OR OR

Bit Clear

MoVe Not

Test bits

AND Rd , Rm EOR Rd , Rm ORR Rd , Rm

BIC Rd , Rm

MVN Rd , Rm

TST Rn , Rm

Rd:=Rd AND Rm Rd:=Rd EOR Rm Rd:=Rd OR Rm

Rd:=Rd AND NOT Rm

Rd:=NOT Rm

Update CPSR Flags on Rn AND Rm

Shift/Rotate

Logical shift left immediate Logical shift right immediate Arithmetic shift right immediate

Rotate right immediate

LSL Rd , Rm , #<immed_5> LSL Rd , Rs

LSR Rd , Rm , #<immed_5> LSR Rd , Rs

ASR Rd , Rm , #<immed_5> ASR Rd , Rs

ROR Rd , Rs

Rd:=Rm<<immed_5

Rd:=Rd<<Rs

Rd:=Rm>>immed_5

Rd:=Rd>>Rs

Rd:=Rm ASR immed_5

Rd:=Rd ASR Rs

Rd:=Rd ROR Rs

5-bit immediate shift. Allowed shifts 0~31

5-bit immediate shift. Allowed shifts 1~32

5-bit immediate shift. Allowed shifts 1~32

Branch

Conditional branch Unconditional branch long branch with link

B{cond} label

B label

BL label

R15:=label

R15:=label

R14:=R15-2 , R15:=label

Label must be within –252 to +258 bytes of current instuction

Label must be within ± 2Kb of current

instuction

Encoded as two Thumb instructions

Label must be within ± 4Mb of current instuction

509

Branch and exchange

Branch with link and exchange

Branch with link and exchange

BX Rm

BLX label

BLX Rm

R15:=Rm AND 0xFFFFFFFE

R14:=R15-2 , R15:=label , change to ARM

R14:=R15-2 , R15:=Rm AND 0xFFFFFFFFE , change to ARM if Rm[0] is 0

Change to Arm state if Rm[0]=0

Encoded as two Thumb instructions

Label must be within ± 4Mb of current instuction

Software

interrupt

SWI<immed_8>

Software interrupt processor exception

8-bit immediate value encoded in instruction

Breakpoint

5T

BKPT< immed_8>

Prefetch abort or enter debug state

Load

With immediate offset , word

Halfword byte

With register offset , word halfword

signed byte

Signed byte PC-relative SP-relative

Multiple

LDR Rd , [Rn , #< immed_5*4>]

LDRH Rd , [Rn , #< immed_5*2>] LDRB Rd , [Rn , #< immed_5>] LDR Rd , [Rn , Rm]

LDRH Rd , [Rn , Rm]

LDRSH Rd , [Rn , Rm] LDRB Rd , [Rn , Rm] LDRSB Rd , [Rn , Rm]

LDR Rd , [PC , #< immed_8*4>] LDR Rd , [SP , #< immed_8*4>]

LDMIA Rn!, < register>

Rd:=[Rn+immed_5*4]

Rd:=ZeroExtend([Rn+immed_5*2][15:0]) Rd:=ZeroExtend([Rn+immed_5][7:0]) Rd:=[Rn+Rm] Rd:=ZeroExtend([Rn+Rm][15:0]) Rd:=SignExtend([Rn+Rm][15:0]) Rd:=ZeroExtend([Rn+Rm][7:0]) Rd:=SignExtend([Rn+Rm][7:0])

Rd:=[(PC AND 0xFFFFFFFC)+immed_8*4] Rd:=[SP+immed_8*4]

Loads list of registers

Clears bits 31:16

Clears bits 31:8

Clears bits 31:16

Sets bits 31:16 to bit 15

Clear bits 31:8

Sets bits 31:8 to bit 7

Always updates base register

Store

With immediate offset , word halfword

byte

With register offset , word halfword

STR Rd , [Rn , #< immed_5*4>] STRH Rd , [Rn , #< immed_5*2>] STRB Rd , [Rn , #< immed_5>]

STR Rd , [Rn , Rm]

STRH Rd , [Rn , Rm]

[Rn+immed_5*4] := Rd [Rn+immed_5*2][15:0] := Rd[15:0] [Rn+immed_5][7:0] := Rd[7:0]

[Rn+Rm] := Rd

[Rn+Rm][15:0] := Rd[15:0]

Ignores Rd[31:16] Ignores Rd[31:8]

Ignores Rd[31:16]

510

byte

SP-relative

Multiple

STRB Rd , [Rn , Rm]

STR Rd , [SP , #< immed_8*4>] STMIA Rn!, < register>

[Rn+Rm][7:0] := Rd[7:0] [SP+immed_8*4] := Rd

Stores list of registers

Ignores Rd[31:8]

Always updates base register

Push/Pop

Push

Push with link

Pop

Pop and return

Pop and return with exchange

5T

PUSH < register> PUSH < register , LR> POP < register>

POP < register , PC>

POP < register , PC>

Push registers onto stack

Push LR and registers onto stack

POP registers from stack

POP registers , branch to address loaded to PC

Push registers , branch , and change to ARM state if address[0] =0

Full descending stack

511