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附录 A ARM 指令集、ARM 寻址方式和 Thumb 指令集速查表

嵌入式系统(修订本)——Intel XScale 结构与开发 陈章龙 著

表A-1 ARM 指令速查表

表中符号说明

{cond}

参见A-2 条件码字段

<oprnd2>

参见A-2 第二操作码

<fields>

参见A-2 PSR 字段

{S}

更新标志位

C*,V*

Flag is unpredicatable after these instructions in Architechure v4 and

earlier

Q

Sticky flag. Always updates on overflow( no S option) . Read and reset

using MRS and MSR

x,y

B:register[15:0],T:register[31:16]

<immed_8r>

A 32-bit constant , formed by right-rotating an 8-bit value by an even

number of bits

<immed_8*4>

A 10-bit constant , formed by shift-rotating an 8-bit value by two bits

功能

§

汇编指令

S 更新

Q

操作

注释

传送

Move

NOT

SPSR 至寄存器

3

MOV {cond } {S} Rd , <Oprnd2> MVN {cond } {S} Rd , <Oprnd2>

MRS {cond } Rd , SPSR

N Z C N Z C

Rd:=Oprnd2

Rd:=0xFFFFFFFF EOR Oprnd2

Rd:=SPSR

500

CPSR 至寄存器

3

MRS {cond } Rd , CPSR

Rd:=CPSR

寄存器至SPSR

寄存器至CPSR 立即数至SPSR 立即数至CPSR

3

3

3

3

MSR {cond } SPSR_<fields>, Rm

MSR {cond } CPSR_<fields>, Rm

MSR {cond } SPSR_<fields>, #<immed_8r> MSR {cond } CPSR_<fields>, #<immed_8r>

SPSR:=Rm(selected bytes only) CPSR:=Rm(selected bytes only) SPSR:=immed_8r(selected bytes only)

CPSR:= immed_8r(selected bytes only)

算术

加法

带进位 饱和加 饱和乘2 加

减法

带进位 反减 带进位反减 饱和减

饱和乘2 减 乘法

乘加

无符号长整数乘法 无符号长整数乘加

有符号长整数乘法 有符号长整数乘加

有符号16*16 乘法 有符号32*16 乘法

5E

5E

5E

5E

2

2

M M M M

5E

5E

ADD {cond } {S} Rd , Rn , <Oprand2> ADC {cond } {S} Rd , Rn , <Oprand2> QADD {cond } Rd , Rm , Rn

QDADD {cond } Rd , Rm , Rn

SUB {cond } {S} Rd , Rn , <Oprand2> SBC {cond } {S} Rd , Rn , <Oprand2> RSB {cond } {S} Rd , Rn , <Oprand2> RSS {cond } {S} Rd , Rn , <Oprand2> QSUB {cond } Rd , Rm , Rn

QDSUB {cond } Rd , Rm , Rn

MUL {cond } {S} Rd , Rm , Rs

MLA {cond } {S} Rd , Rm , Rs , Rn

UMULL {cond } {S} RdLo , RdHi , Rm , Rs

UMLA L{cond } {S} RdLo , RdHi , Rm , Rs

SMULL {cond } {S} RdLo , RdHi , Rm , Rs

SMLA L{cond } {S} RdLo , RdHi , Rm , Rs

SMULxy {cond } Rd , Rm , Rs

SMULWy {cond } Rd , Rm , Rs

N Z C V N Z C V

N Z C V N Z C V N Z C V N Z C V

N Z C* N Z C*

N Z C* V* N Z C* V*

N Z C* V* N Z C* V*

Q Q

Q Q

Rd:=Rn + Oprnd2

Rd:=Rn + Oprnd2 + Carry Rd:=SAT( Rm + Rn ) Rd:=SAT( Rm + SAT(Rn*2) )

Rd:=Rn — Oprnd2

Rd:=Rn — Oprnd2 — NOT(Carry) Rd:= Oprnd2 — Rn

Rd:= Oprnd2 — Rn — NOT(Carry) Rd:=SAT( Rm — Rn )

Rd:=SAT( Rm — SAT(Rn*2) ) Rd:=(Rm*Rs)[31:0] Rd:=((Rm*Rs)+Rn)[31:0]

RdHi , RdLo:=unsigned(Rm*Rs)

RdHi , RdLo:=unsigned(RdHi , RdLo+Rm*Rs)

RdHi , RdLo:= signed(Rm*Rs)

RdHi , RdLo:= signed(RdHi , RdLo+Rm*Rs)

Rd:= Rm[x]*Rs[y]

Rd:= (Rm[x]*Rs[y])[47:16]

No shift/rotate

No shift/rotate

No shift/rotate

No shift/rotate

No shift/rotate

No shift/rotate

501

5E SMLAxy {cond } Rd , Rm , Rs , Rn Q Rd:= Rn + Rm[x]*Rs[y] No shift/rotate

502

带链接和交换(2)

5T

BLX{cond} Rm

R14:=R15-4 , R15:=Rm[31:1] , change to

Thumb if Rm[0] is 1

Load

字读取

用户模式 转移(交换)

字节读取 用户模式 有符号数 半字 有符号数

Pop 或块数据读取 返回(交换)

保存CPSR

寄存器(用户模式下)

4

4

4

LDR{cond} Rd , <a_mode2> LDR{cond} T Rd , <a_mode2P> LDR{cond} R15 , <a_mode2>

LDR{cond} B Rd , <a_mode2> LDR{cond} BT Rd , <a_mode2P> LDR{cond} SB Rd, <a_mode3> LDR{cond} H Rd , <a_mode3> LDR{cond} SH Rd , <a_mode3>

LDM{cond} <a_mode4L> Rd{!} ,<reglist-PC> LDM{cond} <a_mode4L> Rd{!} ,<reglist+PC>

LDM{cond} <a_mode4L> Rd{!} ,<reglist+PC>^

LDM{cond} <a_mode4L> Rd{!} ,<reglist-PC>^

Rd:=[address]

Rd:=[address][31:1]

(§5T:Change to Thumb if [address][0] is 1) Rd:=ZeroExtend[byte from address]

Rd:=SignExtend[byte from address] Rd:=ZeroExtend[halfword from address] Rd:=SignExtend[halfword from address]

Load list of registers from [Rd]

Load registers, R15:=[address][31:1] (§5T:Change to Thumb if [address][0] is 1) Load registers, branch(§5T:and exchange) ,

CPSR:=SPSR

Load list of User mode register to [Rd]

Use from exception mode only

Use from privileged

mode only

Store

字存储

用户模式 字节存储

用户模式 半字存储

Push, 或块数据存储

4

STR{cond} Rd , <a_mode2> STR{cond} T Rd , <a_mode2P> STR{cond} B Rd, <a_mode2> STR{cond} BT Rd , <a_mode2P> STR{cond} H Rd , <a_mode3>

STM{cond} <a_mode4S> Rd{!} ,<reglist>

[address]:=Rd [address]:=Rd [address][7:0]:=Rd[7:0] [address][7:0]:=Rd[7:0] [address][15:0]:=Rd[15:0] Store list of registers to [Rd]

503

寄存器(用户模式下)

STM{cond} <a_mode4L> Rd{!} ,<reglist>^

Store list of User mode registers to [Rd]

Use from privileged

mode only

交换

字交换

字节交换

3

3

SWP{cond} Rd , Rm , [Rn] SWP{cond} B Rd , Rm , [Rn]

Temp:=[Rn] , [Rn]:=Rm , Rd:=temp

Temp:=ZeroExtend([Rn][7:0]) , [Rn][7:0]:=Rm , Rd:=temp

协处理器

数据运算

ARM 寄存器至协处理器 协处理器至 ARM 寄存

器 存储器至协处理器

协处理器至存储器

2

5

2

5

2

5

2

5

2

5

CDP{cond} P <cpnum>,<op1>CRd , CRn , CRm , <op2> CDP2 P <cpnum>,<op1>CRd , CRn , CRm , <op2> MRC{cond} P <cpnum>,<op1>CRd , CRn , CRm , <op2> MRC2 P <cpnum>,<op1>CRd , CRn , CRm , <op2> MCR{cond} P <cpnum>,<op1>CRd , CRn , CRm , <op2>

MCR2 P <cpnum>,<op1>CRd , CRn , CRm , <op2> LDC{cond} P <cpnum>, CRd , <a_mode5>

LDC2 P <cpnum>,CRd , <a_mode5> STC{cond} P <cpnum>, CRd , <a_mode5>

STC2 P <cpnum>,CRd , <a_mode5>

Cannot be conditional

Cannot be conditional

Cannot be conditional

Cannot be conditional

Cannot be conditional

软件中断

SWI{cond}<immed_24>

Software interrupt exception

24-bit value encoded

in instruction

断点

5

BKPT <immed_16>

Prefetch abort or enter debug state

Cannot be conditional

504